Career Profile

Graduated from Pohang Jecheol High School in 2015 and Hanyang University in 2021. After four years of professional experience, I enrolled in a graduate program at Postech. My undergraduate major was Biomedical Engineering, with a minor in Electronic Engineering. I will be joining the CAD & SoC Design Lab at Postech starting in September 2025. My main areas of interest are Deep Learning Hardware, FPGA Implementation, and Model Compression.

Experiences

Application Specific Integrated Circuit Design Engineer

2022 - 2024
LX Semicon, Seoul / DaeJeon

Digital IP Design for MCU Project

Hardware Engineer

2021
Vieworks, AnYang

Panel analysis, PCB circuit verification, product (X-Ray Detector) testing

Embedded Software Engineer

2020.9 - 2020.12
Geo-Line, Seoul

Development of embedded software for electric vehicle chargers

Skills & Proficiency

Python

C / C++

Verilog

HLS (High Level Synthesis)

FPGA